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[VHDL-FPGA-Verilog] pll

Description: 是quartus2的仿真倍频电路，用于产生倍频时钟！-Is a multiplier circuit simulation quartus
Platform: | Size: 332800 | Author: 张宏伟 | Hits:

[Other] MUL

Description: 8-bit modified Booth s algorithm multiplier
Platform: | Size: 80896 | Author: calvin | Hits:

[VHDL-FPGA-Verilog] ALU

Description: VHDL实现cpu核心逻辑与运算单元模块的实现，完成4bit*4bit输入8bit输出的运算，可做加减乘除逻辑移位6种操作-the implementation of Arithmetic and logic unit based on VHDL, can do as the adder,subtractor,multiplier,divider,shifter and logic operation.
Platform: | Size: 619520 | Author: caolei | Hits:

[VHDL-FPGA-Verilog] mul24x24

Description: 24位x24位的乘法器 十分详细24位x24位的乘法器24位 x24位的乘法器24位 x24位的乘法器24位 x24位的乘法器24位x24位的乘法器-24-bit x24-bit multiplier very detailed 24-bit x24-bit 24-bit x24-bit multiplier of the multiplier 24-bit x24-bit 24-bit x24-bit multiplier of the multiplier 24-bit x24-bit 24-bit x24-bit multiplier of the multiplication Explorer 24-bit x24 multiplier 24-bit x24-bit multiplier
Platform: | Size: 14336 | Author: zhb | Hits:

[VHDL-FPGA-Verilog] mux4

Description: 四位乘法器的VHDL语言设计，并有原理图的描述-4 Multiplier VHDL language design, and schematic description of
Platform: | Size: 203776 | Author: 望天 | Hits:

[VHDL-FPGA-Verilog] 4multiplier

Description: 4位乘法器vhdl程序-- DESCRIPTION : Signed mulitplier:-- A (A) input width : 4-- B (B) input width : 4-- Q (data_out) output width : 7-4 multiplier vhdl procedure
Platform: | Size: 3072 | Author: lsp | Hits:

[Other] e

Description: 《EDA技术实用教程》实验选编 专题一：计数分频器设计 4 专题二：存储器定制 7 实验一：快速乘法器电路设计 11 实验二：高速数字相关器设计 17 实验三：TLC5510高速A/D转换器控制 21 实验四：直接数字频率合成器（DDFS）设计 23 实验五：基于直接数字频率合成技术的任意波形发生器-" EDA technology practical course" Selected experimental one topic: the design count crossovers feature 4 2: 7 experiment a custom memory: Fast multiplier circuit design of 11 experiments II: the design of high-speed digital correlator 17, the experiment three: TLC5510 high-speed A/D converter control 21 of the experiment four: Direct Digital Frequency Synthesizer (DDFS) experimental design, 23 5: Based on Direct Digital Synthesis technology, arbitrary waveform generator
Platform: | Size: 2693120 | Author: 耿守浩 | Hits:

[VHDL-FPGA-Verilog] Multiplier

Description: 4 bit multiplier written in behavioral VHDL, using logic gate logic. inputs are A and B (4 bit each) and output is C (8 bits).
Platform: | Size: 1024 | Author: avi | Hits:

[VHDL-FPGA-Verilog] 4bitMultiplier

Description: 4 bit multiplier implemented with behavioral VHDL code. in addition a visio shceme is attached along with a jpg copy for thoese fho dont have visio.
Platform: | Size: 136192 | Author: avi | Hits:

[VHDL-FPGA-Verilog] multi

Description: VHDL Multiplier RTL code-VHDL Multiplier RTL code
Platform: | Size: 2048 | Author: Anil Kumar Saini | Hits:

[Other] Parallel_Booth_Multiplier

Description: Parallel Booth Multiplier Circuit in VHDL
Platform: | Size: 11264 | Author: Carlos H Nacer | Hits:

[VHDL-FPGA-Verilog] lunwen

Description: 潘明海　刘英哲　于维双 (论文) 中文摘要： 本文讨论了一种可在FPGA上实现的FFT结构。该结构采用基于流水线结构和快速并行乘法器的蝶形处理器。乘法器采用改进的Booth算法，简化了部分积符号扩展，使用Wallace树结构和4-2压缩器对部分积归约。以8点复点FFT为实例设计相应的控制电路。使用VHDL语言完成设计，并综合到FPGA中。从综合的结果看该结构可在XC4025E-2上以52MHz的时钟高速运行。在此基础上易于扩展为大点数FFT运算结构。 -Pan Minghai Liuying Zhe Yu-dimensional pairs (thesis) Chinese Abstract: This paper discusses an FPGA can be implemented on the structure of the FFT. The architecture based on pipeline architecture and fast parallel multiplier butterfly processor. Multiplier using modified Booth algorithm simplifying the partial product sign extension, use the Wallace tree and 4-2 compressor for partial product reduction. 8-point complex-point FFT as an example design of the corresponding control circuit. To complete the design using the VHDL language, and integrated into the FPGA. From the results of a comprehensive look at the structure can be XC4025E-2 with 52MHz clock on the high-speed operation. On this basis, easy to expand the structure for large point FFT operations.
Platform: | Size: 128000 | Author: culun | Hits:

[VHDL-FPGA-Verilog] mutiplier

Description: 用VHDL语言仿真乘法器设计, 经过modelsim仿真， synplify综合，并下载进FPGA验证-Multiplier design using VHDL, simulation, after modelsim simulation, synplify synthesis, and downloaded into a FPGA verification
Platform: | Size: 222208 | Author: 赵牧 | Hits:

[VHDL-FPGA-Verilog] cheng1

Description: 用VHDL实现十六位移位乘法器 才有移位相加法来实现-Use VHDL to achieve 16-bit shift multiplier shift only the sum of law to achieve
Platform: | Size: 26624 | Author: 齐娜 | Hits:

[Crack Hack] freehdl-0.0.6.tar

Description: inplementation of AES vhdl The use of a list of law, VHDL language based polynomial-based finite field multiplier, for the AES algorithm
Platform: | Size: 1391616 | Author: tarik | Hits:

[VHDL-FPGA-Verilog] wallace

Description: This a code for wallace tree multiplier-This is a code for wallace tree multiplier
Platform: | Size: 4096 | Author: vlsi | Hits:

[VHDL-FPGA-Verilog] liushuixian_mul

Description: 流水线乘法器的VHDL实现，希望对你会有用！-Pipelined multiplier in VHDL implementation, you will want to use!
Platform: | Size: 3072 | Author: snow | Hits:

[VHDL-FPGA-Verilog] multiplexer

Description: 几种常用乘法器的Verilog、VHDL代码-Several common multiplier Verilog, VHDL code
Platform: | Size: 267264 | Author: kk | Hits:

[VHDL-FPGA-Verilog] code

Description: This project is "digital serial multiplier". this proh=ject is used to multiply the serial data with parallel data. the source code is writtenby using vhdl.
Platform: | Size: 5120 | Author: RUPA KRISHNA | Hits:

[source in ebook] Chapter1-5

Description: 第一章到第五章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter to Chapter V of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, function authentication, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 1580032 | Author: xiao | Hits:
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